"i do disable interrupt for a while.
and do some heavy ISR."
Then, my above "theory" is feasibly applied to your case.
To make it sure, confirm it actually occurs.
- At the entry of the SMBus ISR, pull a spare port pin to low
- At the exit of the SMBus ISR, put high to the pin.
Then the port pin shows the execution of SMBus ISR.
Observing SCL and this pin on a scope, you'll know how long SMBus interrupt is delayed, when SCL is kept low.
The execution time of the SMBus ISR may be too short to observe it on the scope with SCL.
In this case, flip the pin just at the entry of the SMBus ISR.
Then the rising and falling edge of this pin shows the start of the SMBus ISR."however, why does it happen only with certain masters and not all?"
The delay is caused by your heavy ISR and/or the routine which disable interrupt.
The next step is specifying the routine which causes this delay.
You can apply above pin method to each suspicious routine or ISR.
Now the question is converted to this one.
Why this routine takes so much time just for specific inputs?
The answer surely lies in your source code of this routine
Making the interrupt priority of SMBus to high and the heavy ISR to low, you'll temporarily treat this delayed interrupt problem. But I recommend you to specify the real cause, and fix it radically.
[This message has been edited by Tsuneo (edited September 23, 2008).]